[MUSIC]. In this lesson, we are going to give some information about integrated circuit implementation strategies and about synthesis tools. The conclusion of the preceding lesson was that the design of an integrated circuit is a very complex task. In the case of large circuits, millions of geometrics forms must be laid out. So, it is essential to use specific implementation strategies and to have software synthesis tools. First, let us talk about implementation strategies. Three of them are presented. The first one is the Standard Cell approach. It is based on libraries of cells, cells such as logic gates, flip flops, mulitplexers, registers and so on. The layout of each cell is generated in advance and stored within a cell library, and all the cells must have the same height. Here is an example. This is the layout of 3-input NAND gate with three n-type transistor in this part and three p-type transistor in parallel in this area. Then, the layout of the circuit is generated automatically, placing the cells in rows; this is possible because all cells have the same height. Furthermore, macrocells can also be added to the circuit, for example memory blocks or multipliers. The resulting floor plan is of this type: rows of cells like this one separated by routing channels used to lay out the connections. And in many cases, there are also some macrocells. In fact, in modern circuits, there are no routing channels and additional metal layers are used to layout connections on top of the cells. This is part of a standard cell design with interconnections on top of the cells. The second implementation strategy is based on Gate Array components. In this case, arrays of cells manufactured in advance, without regard to the final application, and only the desired connections must be added, in function of the application. The floor plan is similar to the floor plan of a Standard Cell circuit, but to a particular Gate Array component corresponds a predefined floor plan. For example, the number of rows, the size of the rows, the distance between rows, and so, on cannot be modified. On the other hand, Gate Array vendors offer families of components with different gate number capacities and input/output pin numbers. The rows are constituted of uncommitted cells and the space between rows is used to lay out connections. Here is an example of uncommitted cell with four p-type transistors and four n-type transistors. The red tracks (here) correspond to the current gates of the four transistor pairs. As an example, to implement a 4-input NOR gate, some additional metal connections must be added. You can see that in this circuit the four p-type transistors are connected in series between power supply and output, and that the four n-type transistors are connected in parallel between output and ground. Output, ground; output, ground; and output, ground. This is a 4-input NOR gate. As in the case of the standard cell approach, in modern Gate Arrays there are no more routing channels and the connections are laid out on top of the cells. The third strategy is Field Programmable Gate Arrays. It is similar to a Gate Array, but it is user-programmable. The floor plan is of this type. It is set of programmable basic cells and a lot of programmable connections: basic cells and programmable connections. This is an example of very simplified basic cell. It includes a look-up table able to implement any 4-variables switching function and a flip flop. Thank to this multiplexer, the cell output is either the look-up table output or the flip flop output. The table contents and the configuration bits are like memory bits. So, apart from the basic cell and from the connections, an FPGA also includes a lot of stored configuration data, as if it were a static RAM or an E2PROM for example. As regards the connections, here are three examples of programmable connections between an horizontal line and a vertical line. The first example is a transistor controlled by a configuration bit. A second example is an antifuse, that is a switch initially open, but that can be shortcircuited by applying a high voltage. And the third example is a floating gate transistor: according to the electric charges on the floating gate, this transistor conducts or doesn't. This is an example of commercial gate array including not only basic cells, called Configurable Logic Blocks in this example, but also RAM blocks and multipliers (here). Modern FPGA are very large circuits, that allow implementing complete systems on a chip, including Microprocessors and Memory blocks. They constitute a very good option to integrate prototypes or also in the case of the relatively low quantity production. Now, some comments about Synthesis tools. First, let us introduce the concept of Register Transfer Level description. It is a functional description, for example, in some Hardware Description Language, but not any type of functional description is an RTL description. The operation executed during each clock period must be defined. An example is the programmable timer described last week. It is a functional description (it doesn't include any reference to gates or to flip-flops), but it specifies what operation are performed at each clock pulse. This is the concept of Register Transfer Level description. Once an RT-level description has been defined and tested, for example, by simulation, a Logic Synthesis tool may be used. The synthesis is done in two steps: first, from an RTL description to a technology independent circuit structure; with gates, flip-flops and so on, but without specifying the target technology. And then, the second stage, from the technology independent structure to a structure using cells of the selected library, either a Standard Cell or a Gate Array or an FPGA library. After logic synthesis, physical implementation tools are used. They generate the implementation data from the structural description. And two important types of physical implementation are ASIC (Application Specific Integrated Circuits) based (for example) on Standard Cell or Gate Grray cell libraries. And a second type is Field Programmable Gate Array that is a user programmable component. Whatever the chosen technology, the two following operations must be performed. First, the Placement, that is the assignment of positions to the used library cells. And then the Routing, that is, the layout of the connections. Summary. The subject of this lesson were implementation strategies and three of them have been described: Standard Cell, Gate Arrays, and FPGAs; Logic Synthesis tools and finally Physical Implementation tools. [BLANK_AUDIO]
